The present invention generally relates to semiconductor integrated circuits, and more particularly, to a method and structure for simultaneously forming integrated capacitors with nanosheet channel field effect transistors.
CMOS is used for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS designs may use complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions.
The MOSFET is a transistor used for switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or high dielectric constant (high-k) dielectrics, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
Decoupling capacitors are a type of capacitor used to decouple one part of an electrical network (circuit) from another. Noise caused by other circuit elements is shunted through the capacitor, reducing the effect it has on the rest of the circuit. An alternative name is bypass capacitor as it is used to bypass the power supply or other high impedance component of a circuit.
As integrated circuits continue to scale down and become more densely built, nanosheet field effect transistors (FETs) are an attractive alternative to Fin FETs or planar devices for future CMOS nodes.